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DATA SHEET
2GB Registered SDRAM DIMM
EBS21RC2ACNA (256M words x 72 bits, 2 banks)
Description
The EBS21RC2ACNA is 256M words x 72 bits, 2 banks Synchronous Dynamic RAM Registered Module, mounted 72 pieces of 256M bits SDRAM sealed in TCP package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
Features
* Fully compatible with 8 bytes DIMM: JEDEC standard outline * 168-pin socket type dual in line memory module (DIMM) PCB height: 41.91mm (1.65inch ) Lead pitch: 1.27mm * 3.3V power supply * Clock frequency: 133MHz (max.) * LVTTL interface * Data bus width: x 72 ECC * Single pulsed /RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length (BL): 1, 2, 4, 8 * 2 variations of burst sequence Sequential Interleave * Programmable /CAS latency (CL): 2, 3 * Registered inputs with one clock delay * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64ms * 2 variations of refresh Auto refresh Self refresh * 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2k bits) for Presence Detect (SPD) on PCB.
Document No. E0105E50 (Ver. 5.0) Date Published June 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002
EBS21RC2ACNA
Ordering Information
Part number EBS21RC2ACNA-7A EBS21RC2ACNA-75*1 Clock frequency MHz (max.) 133 133 /CAS latency 2, 3 3 Package 168-pin DIMM Contact pad Gold Mounted devices 256M bits SDRAM TCP*2
Note: 1. 100MHz operation at /CAS latency = 2. 2. Please refer to the TSOP products EDS25XXACTA datasheet (E0277E) for detail information.
Pin Configurations
1 pin 10 pin 11 pin 40 pin 41 pin 84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE DQMB0 DQMB1
Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
Pin name VSS NC /CS2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26
Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQMB4 DQMB5
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
Pin name VSS CKE0 /CS3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58
Data Sheet E0105E50 (Ver. 5.0)
2
EBS21RC2ACNA
Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name /CS0 NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VDD VDD CLK0 Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VDD Pin No. 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 Pin No. 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VDD
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /CS0 to /CS3 /RAS /CAS /WE DQMB0 to DQMB7 CLK0 to CLK3 CKE0 REGE* SDA SCL SA0 to SA2 VDD VSS NC
1
Function Address input Row address A0 to A12 Column address A0 to A9, A11, A12 Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (/RAS) input Column enable (/CAS) input Write enable input Byte data mask Clock input Clock enable input Register/Buffer enable Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
Note: 1. REGE VIH: Register mode. REGE VIL: Buffer mode.
Data Sheet E0105E50 (Ver. 5.0)
3
EBS21RC2ACNA
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels SDRAM cycle time (highest /CAS latency) 7.5ns SDRAM access from Clock (highest /CAS latency) 5.4ns Module configuration type Refresh rate/type SDRAM width Error checking SDRAM width SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM device attributes SDRAM device attributes: General SDRAM cycle time (2nd highest /CAS latency) (-7A) 7.5ns (-75) 10ns SDRAM access from Clock (2nd highest /CAS latency) (-7A)5.4ns (-75) 6ns SDRAM cycle time (3rd highest /CAS latency) Undefined SDRAM access from Clock (3rd highest /CAS latency) Undefined
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 80H 08H 04H 0DH 0CH 02H 48H 00H 01H 75H
Comments 128 256 byte SDRAM 13 12 2 72 bit 0 (+) LVTTL CL = 3*5
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0
1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0
1 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0
0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0
0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 0 0
54H 02H 82H 02H 02H 01H 0FH 04H 06H 01H 01H 1FH 0EH 75H A0H 54H 60H 00H ECC Normal (7.8125 s) Self refresh 128M x 2 x2 1 CLK 1, 2, 4, 8 4 2, 3 0 0 Registered VDD 10% CL = 2*5
24
25
26
0
0
0
0
0
0
0
0
00H
Data Sheet E0105E50 (Ver. 5.0)
4
EBS21RC2ACNA
Byte No. 27
Function described Minimum row precharge time (-7A) (-75)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 x 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 x 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 1 0 x 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 x 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 0 x 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 x 0 1 1 1 0 1 1 1 0 1 1 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 x 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0FH 14H 0FH 0FH 14H 2DH 01H 15H 08H 15H 08H 00H 3CH 43H 00H 12H 36H 7EH 7FH FEH 00H xx 45H 42H 53H 32H 31H 52H 43H 32H 41H 43H 4EH 41H 2DH 37H 41H 35H 20H
Comments 15ns 20ns 15ns 15ns 20ns 45ns 2 bank 1G byte 1.5ns*5 0.8ns*5 1.5ns*5 0.8ns*5 Future use 60ns 67.5ns Future use Rev. 1.2 54 126 Continuation code Elpida Memory
28 29
Row active to row active min /RAS to /CAS delay min (-7A) (-75)
30 31 32 33 34 35 36 to 40 41
Minimum /RAS pulse width Density of each bank on module Address and command signal input setup time Address and command signal input hold time Data signal input setup time Data signal input hold time Superset information Minimum bank Cycle (-7A) (-75)
42 to 61 62 63
Superset information SPD data revision code Checksum for bytes 0-62 (-7A) (-75)
64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-7A) (-75)
*2 (ASCII-8bit code) E B S 2 1 R C 2 A C N A -- 7 A 5 (Space)
88
Manufacturer's part number
Data Sheet E0105E50 (Ver. 5.0)
5
EBS21RC2ACNA
Byte No. 89 90 91 92 93 94 95 to 98 99 to 125 126 127 Function described Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Assembly serial number Manufacturer specific data Reserved (Intel specification frequency) Reserved (Intel specification /CAS# latency support) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value 0 0 0 0 x x *
3
Comments (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
0 0 0 0 x x
1 1 1 1 x x
0 0 1 0 x x
0 0 0 0 x x
0 0 0 0 x x
0 0 0 0 x x
0 0 0 0 x x
20H 20H 30H 20H xx xx
-- 0 1
-- 1 0
-- 1 0
-- 0 0
-- 0 0
-- 1 1
-- 0 1
-- 0 1
-- 64H 87H
*4
Notes: 1. All serial PD data are not protected. 0: Serial data, "Low", 1: Serial data, "High". 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0"). 5. These specifications are defined based on component specification, not module.
Data Sheet E0105E50 (Ver. 5.0)
6
EBS21RC2ACNA
Block Diagram
/RCS0 /RCS1 RDQMB0 DQMB /CS 4 DQ0 to DQ3
10
RDQMB4 DQMB /CS DQMB /CS 4 DQ32 to DQ35
10
DQMB /CS
D0/D1
I/O0, I/O1 DQMB /CS
D36/D37
I/O0, I/O1 DQMB /CS
D18/D19
I/O0, I/O1 DQMB /CS
D54/D55
I/O0, I/O1 DQMB /CS
4 DQ4 to DQ7 RDQMB1
10
D2/D3
I/O0, I/O1
D38/D39
I/O0, I/O1 DQ36 to DQ39 RDQMB5
4
10
D20/D21
I/O0, I/O1
D56/D57
I/O0, I/O1
DQMB /CS 4 DQ8 to DQ11
10
DQMB /CS
DQMB /CS 4 DQ40 to DQ43
10
DQMB /CS
D4/D5
I/O0, I/O1 DQMB /CS
D40/D41
I/O0, I/O1 DQMB /CS
D22/D23
I/O0, I/O1 DQMB /CS
D58/D59
I/O0, I/O1 DQMB /CS
4 DQ12 to DQ15
10
D6/D7
I/O0, I/O1 DQMB /CS
D42/D43
I/O0, I/O1 DQMB /CS DQ44 to DQ47
4
10
D24/D25
I/O0, I/O1 DQMB /CS
D60/D61
I/O0, I/O1 DQMB /CS
CB0 to CB3 /RCS2 /RCS3 RDQMB2
4
10
D8/D9
I/O0, I/O1
D44/D45
I/O0, I/O1 CB4 to CB7
4
10
D26/D27
I/O0, I/O1
D62/D63
I/O0, I/O1
RDQMB6 DQMB /CS 4
10
DQMB /CS
DQMB /CS 4 DQ48 to DQ51
10
DQMB /CS
D10/D11
I/O0, I/O1 DQMB /CS
D46/D47
I/O0, I/O1 DQMB /CS
D28/D29
I/O0, I/O1 DQMB /CS
D64/D65
I/O0, I/O1 DQMB /CS
DQ16 to DQ19
DQ20 to DQ23 RDQMB3
4
10
D12/D13
I/O0, I/O1
D48/D49
I/O0, I/O1 DQ52 to DQ55 RDQMB7
4
10
D30/D31
I/O0, I/O1
D66/D67
I/O0, I/O1
DQMB /CS 4 DQ24 to DQ27
10
DQMB /CS
DQMB /CS 4 DQ56 to DQ59
10
DQMB /CS
D14/D15
I/O0, I/O1 DQMB /CS
D50/D51
I/O0, I/O1 DQMB /CS
D32/D33
I/O0, I/O1 DQMB /CS
D68/D69
I/O0, I/O1 DQMB /CS
4 DQ28 to DQ31
10
D16/D17
I/O0, I/O1
D52/D53
I/O0, I/O1 DQ60 to DQ63
4
10
D34/D35
I/O0, I/O1
10
D70/D71
I/O0, I/O1
CLK0 /CS0, /CS1, /CS2, /CS3 DQMB0 to DQMB7 BA0 to BA1 A0 to A12 /RAS /CAS CKE0 /WE
10k
R E G I S T E R
/RCS0, /RCS1, /RCS2, /RCS3 RDQMB0 to RDQMB7 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D71 CLK1 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D71 to CLK3 /RRAS -> /RAS: SDRAMs D0 to D71 /RCAS -> /CAS: SDRAMs D0 to D71 VDD RCKE0 -> CKE: SDRAMs D0 to D71 0.0022F x 41 pcs /RWE -> /WE: SDRAMs D0 to D71 VSS Serial PD SCL SCL SDA SDA
12pF
10
PLL
CLK : SDRAMs (D0 to D71) Register
VSS
12pF
VDD (D0 to D71, U0)
0.22F x 32 pcs VSS (D0 to D71, U0) * D0 to D71: 256M bits SDRAM TCP PLL: 2510 Register: 162834 U0: 2k bits EEPROM
VDD REGE PLL CLK
U0
A0 A1
WP
A2
SA0 SA1 SA2 VSS Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
Data Sheet E0105E50 (Ver. 5.0)
7
EBS21RC2ACNA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to VDD + 0.5 ( 4.6 (max.)) -0.5 to +4.6 50 36.0 0 to +70 -55 to +125 Unit V V mA W C C Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions
Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage Ambient illuminance VIH VIL -- min. 3.0 0 2.0 -0.3 -- max. 3.6 0 VDD + 0.3 0.8 100 Unit V V V V lx Note 1 2 3 4
Notes: 1. 2. 3. 4.
The supply voltage with all VDD pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max.) = VDD + 2.0V for pulse width 3ns at VDD. VIL (min.) = VSS - 2.0V for pulse width 3ns at VSS.
Data Sheet E0105E50 (Ver. 5.0)
8
EBS21RC2ACNA
DC Characteristics 1
Parameter Operating current
Symbol ICC1 ICC1
Grade -7A -75
max. 6455 5735 911 2135 983 2855 6455
Unit mA mA mA mA mA mA mA mA mA mA
Test condition Burst length = 1 tRC = tRC(min.)
Notes 1, 2, 3
Standby current in power down Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current Refresh current
ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC5 -7A -75
CKE = VIL, tCK = 12ns CKE, /CS = VIH, tCK = 12ns CKE = VIL, tCK = 12ns CKE, /CS = VIH, tCK = 12ns tCK = tCK (min.), BL = 4 tRC = tRC(min.) VIH VDD - 0.2V VIL 0.2V
6 4 1, 2, 6 1, 2, 4 1, 2, 5 3
10775 9695 911
Self refresh current
ICC6
7
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After self refresh mode set, self refresh current. DC Characteristics 2
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -10 -10 2.4 -- max. 10 10 -- 0.4 Unit A A V V Test condition 0 VIN VDD 0 VOUT VDD DQ = disable IOH = -4mA IOL = 4mA Notes
Pin Capacitance (TA = 25C, VDD = 3.3V 0.3V)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 CI6 Data input/output capacitance CI/O1 Pins Address /RAS, /CAS, /WE CKE /CS CLK DQMB DQ, CB max. 25 25 25 20 45 20 35 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Notes: 1.Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing. 3. DQMB = VIH to disable Data-out. 4. This parameter is sampled and not 100% tested.
Data Sheet E0105E50 (Ver. 5.0)
9
EBS21RC2ACNA
AC Characteristics (SDRAM device specification)
-7A Parameter System clock cycle time CLK high pulse width CLK low pulse width Access time from CLK Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance Input setup time Input hold time Symbol tCK tCH tCL tAC tOH tLZ tHZ tSI tHI min. 7.5 2.5 2.5 -- 2.7 1 -- 1.5 0.8 60 45 15 15 15 2CLK + 15ns 15 0.5 -- -75 min. 7.5 2.5 2.5 -- 2.7 1 -- 1.5 0.8 67.5 45 20 20 15 2CLK + 20ns 15 0.5 -- max. -- -- -- 5.4 -- -- 5.4 -- -- -- 120000 -- -- -- -- -- 5 64 ns ns ms 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1, 2 1, 2 1, 2, 3 1, 4 1 1 1 1 1 1 1
Ref/Active to Ref/Active command period tRC Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Last data into active latency tRAS tRCD tRP tDPL tDAL
Active (a) to Active (b) command period tRRD Transition time (rise and fall) Refresh period (8192 refresh cycles) tT tREF
Notes: 1. 2. 3. 4.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V. Access time is measured at 1.4V. Load condition is CL = 50pF. tLZ (min.) defines the time at which the outputs achieves the low impedance state. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Test Conditions * Input and output timing reference levels: 1.4V * Input waveform and output load: See following figures
2.4V 0.4V 2.0V 0.8V DQ CL tT
tT
Input Waveform and Output Load
Data Sheet E0105E50 (Ver. 5.0)
10
EBS21RC2ACNA
Relationship Between Frequency and Minimum Latency (SDRAM device specification)
Parameter Frequency (MHz) tCK (ns) /CAS latency Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command /CS to command disable Power down exit to command input Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lDAL lSEC lHZP lAPR lEP lCCD lWCD lDID lDOD lCLE lMRD lCDD lPEC -7A 133 7.5 CL = 3 2 8 6 2 2 2 1 4 8 3 1 -2 1 0 0 2 1 1 0 1 133 7.5 CL = 2 2 8 6 2 2 2 1 4 8 2 1 -1 1 0 0 2 1 1 0 1 -75 133 7.5 CL = 3 3 9 6 3 2 2 1 5 9 3 1 -2 1 0 0 2 1 1 0 1 100 10 CL = 2 2 7 5 2 2 2 1 4 7 2 1 -1 1 0 0 2 1 1 0 1 Notes 1 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
Data Sheet E0105E50 (Ver. 5.0)
11
EBS21RC2ACNA
Pin Functions
CLK0 to CLK3 (input pins): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. /CS0 to /CS3 (input pins): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY9, AY11, AY12) is determined by A0 to A9, A11 or A12 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged. BA0 and BA1 (input pins) BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. CKE0 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins. VDD (power supply pins): 3.3V is applied. VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the EDS2504ACTA/08ACTA/16ACTA datasheet (E0277E).
Data Sheet E0105E50 (Ver. 5.0)
12
EBS21RC2ACNA
Physical Outline
Front side 133.35 3.00 (DATUM -A-) (63.67) 4.80 Max Unit: mm
3.00
Component area (Front)
1 C 11.43 36.83 B 54.61 A 84
Back side 2 - 3.00
127.35
4.00
(DATUM -A-) Detail A 2.50 0.20 1.27 0.050 0.20 0.15 Detail B R FULL Detail C (DATUM -A-) 1.00 R FULL
6.35 3.125 0.125 2.00 0.10 3.125 0.125
6.35 4.175 2.00 0.10
1.00 0.05
Note: Tolerance on all dimensions 0.15 unless otherwise specified.
ECA-TS2-0025-01
Data Sheet E0105E50 (Ver. 5.0)
13
41.91
Component area (Back)
17.80
4.00 Min 1.27 168
85
EBS21RC2ACNA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0105E50 (Ver. 5.0)
14
EBS21RC2ACNA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0105E50 (Ver. 5.0)
15

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